ASIC Physical Design Engineer Staff page is loadedASIC Physical Design Engineer StaffApply locations San Jose, California, United States of America time type Full time posted on Posted 2 Days Ago job requisition id 1191706 ASIC Physical Design Engineer StaffThis role has been designed as ‘Hybrid’ with an expectation that you will work on average 2 days per week from an HPE office.Who We Are:Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.Our culture thrives onfinding new and better ways to accelerate what’s next.We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs.We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you.Open up opportunities with HPE.Job Description:Job Family Definition:Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation, and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits. Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions. May direct support personnel in the preparation of detailed design, design testing and prototype fabrication.Management Level Definition:Contributions have visible technical impact on a product or major subcomponent. Applies in-depth professional knowledge and innovative ideas to solve complex problems. Visible contributions improve time-to-market, achieve cost reductions, or satisfy current and future unmet customer needs. Recognized internal authority on key technology area applying innovative principles and ideas. Provides technical leadership for significant project/program work. Leads or participates in cross-functional initiatives and contributes to mentorship and knowledge sharing across the organization.Responsibilities:Implement physical design at the large SoC chip level from RTL to GDSII, creating a design database ready for manufacturing.Interact with IP vendors to understand IP integration requirements and integrate all blocks, IPs, and sub-chips at a large SoC level.Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement.Build full chip floorplan, including pads/ports/bump placement, block placement and optimization, block pins placement and alignment, power grid, and RDL design, etc.Develop the chip-level clock network and clock stations in collaboration with clock experts.Budget timing among blocks and sub-chips at the chip level, generating block/chip-level static timing constraints.Arrange, analyze, and optimize feedthrough and repeaters among all blocks/sub-chips at the chip level.Perform block-level place and route, ensuring the design meets timing, area, power constraints, and all sign-off criteria.Generate and implement ECOs to fix timing, signal integrity, EM/IR violations, PV, and complete formal verification.Integrate DFT into physical design, ensuring alignment with overall test strategies and manufacturing requirements.Run Physical Design verification flow at chip/block level, fixing LVS/DRC/ERC/ANT violations.Collaborate closely with architecture, frontend design, DV, and package teams to ensure cohesive design implementation and successful project tapeouts.Education and Experience Required:BS degree in electrical engineering, computer engineering, or a related field with 7+ years of experience in block or full-chip physical design, orMS degree in the above fields with 5+ years of related experience.Knowledge and Skills:Deep design experience in large SoC designs, including IP integration, padring design, bump planning, and RDL routing strategy.Extensive knowledge and practices in Physical Design, including physically aware synthesis, floor-planning, place & route, CTS, and repeater/feedthrough.Experience in developing and implementing power-grid and clock network at chip level.Knowledge of basic SoC architecture and HDL languages like Verilog to work with the logic design team for timing fixes.Experience in physical design verification to debug LVS/DRC/ERC/ANT issues at chip/block level.Exposure to 2.5D/3D packaging is preferred.High performance and large chip design experience is preferred.Exposure to DFT is preferred.Proficiency in writing Linux shell scripts in Perl, TCL, and Python.Real chip tapeout experience in 7nm and/or below with a successful signoff track record.Self-motivated with strong problem-solving and debugging skills.Ability to work effectively in a dynamic group environment.Additional Skills:Accountability, Accountability, Action Planning, Active Learning (Inactive), Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}What We Can Offer You:Health & WellbeingWe strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.Personal & Professional DevelopmentWe also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.Unconditional InclusionWe are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.Let's Stay Connected:Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.#unitedstates#aruba, #networkingJob:EngineeringJob Level:TCP_05States with Pay Range RequirementThe expected salary/wage range for a U.S.-based hire filling this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. If this is a sales role, then the listed salary range reflects combined base salary and target-level sales compensation pay. If this is a non-sales role, then the listed salary range reflects base salary only. Variable incentives may also be offered. Information about employee benefits offered can be found at https://myhperewards.com/main/new-hire-enrollment.html .USD Annual Salary: $148,000.00 - $340,500.00HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity .Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.About UsTechnology innovation that fosters business transformation.We help customers use technology to slash the time it takes to turn ideas into value. In turn, they transform industries, markets and lives.Some of our customers run traditional IT environments. Most are transitioning to a secure, cloud-enabled, mobile-friendly infrastructure. Many rely on a combination of both. Wherever they are in that journey, we provide the technology and solutions to help them succeed.COVID PolicyThe health and safety of our team members, customers and partners is paramount at HPE. Accordingly, if applicable to the role you applied to, you must be fully vaccinated against COVID-19 by the employment start date where permitted by law. Exemptions based on medical, religious or other grounds will be processed and approved in accordance with local laws.Standards of Business Conduct (SBC)The Hewlett Packard Enterprise Standards of Business Conduct (SBC) embody the fundamental principles that govern our ethical and legal obligations to Hewlett Packard Enterprise. They pertain not only to our conduct within the company but also to conduct involving our customers, channel partners, suppliers and competitors.Hewlett Packard Enterprise provides equal employment opportunity to any employee or applicant without regard to sex, gender, color, race, ethnicity, religion, creed, national origin, ancestry, citizenship, age, marital status, sexual orientation, gender identity and expression, physical or mental disability, medical condition, pregnancy, protected veteran status, uniformed service status, familial status, genetic information, political affiliation, or any other characteristic protected by federal, state, or local law. Please click here: Equal Employment Opportunity .If you’d like more information about your EEO right as an applicant under the law, please click here:E-Verify (US & PR only)HPE is an E-Verify employer. E-Verify is an Internet-based system that compares information from an employee's Form I-9, Employment Eligibility Verification, to data from U.S. Department of Homeland Security and Social Security Administration records to confirm the employment eligibility of all newly hired employees. For more information click here . You can also download the posters with information on legal rights and protection by clicking here and here .AccessibilityHewlett Packard Enterprise is committed to working with and providing reasonable accommodation to qualified, differently abled individuals. If you need assistance in filling out the employment application or require a reasonable accommodation while seeking employment, please email recruiting@hpe.com .Note: This option is reserved for applicants needingassistance/reasonable accommodation related to a disability.Disclosure of Sensitive Personal DataPlease ensure the resume you submit to us does not include any sensitive personal data.Sensitive personal data includes data revealing information about your racial or ethnic origin, political opinions, religious or philosophical beliefs, trade union membership, health, sex life or sexual orientation.To the extent the resume you submit does contain this type of personal data, you consent to the storing and processing of this data by HPE for the purpose of reviewing and managing your application. #J-18808-Ljbffr