This range is provided by Meta. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range $114,000.00/yr - $166,000.00/yr Meta's Reality Labs (RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state-of-the-art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with an industry-leading group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP or System on Chip (SoC) implementations. You will work closely with researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art IPs or SoCs.

Design Verification Engineer Responsibilities:

Work with researchers and architects defining verification plans for each of the different core IP Define and track detailed test plans for the different modules and top levels Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Minimum Qualifications:

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta 2+ years ASIC development cycle industry experience 2+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology 2+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Preferred Qualifications:

Experience in development of UVM based verification environments from scratch Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs Experience with revision control systems like Mercurial(Hg), Git or SVN Experience with low power design Experience working across and building relationships with cross-functional design, model and emulation teams Master's degree in Computer Science, Computer Engineering, or a related field

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

$114,000/year to $166,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta. Seniority level Seniority level Not Applicable Employment type Employment type Full-time Job function Job function Engineering and Information Technology Industries Technology, Information and Internet Referrals increase your chances of interviewing at Meta by 2x Get notified about new Design Verification Engineer jobs in San Diego, CA . San Diego, CA $122,649.00-$173,400.00 23 hours ago SOC Verification and Methodology Engineer SOC Verification and Methodology Engineer - Sr Staff Senior ASIC Design Verification Engineer (Security Group) Digital ASIC Design Engineer for High-Speed Interfaces Graphics ASICS Hardware Design Engineer (San Diego/Santa Clara/Austin/Boxborough) Analog/Mixed-Signal Design Verification Methodology Development Engineer San Diego, CA $150,000.00-$260,000.00 20 hours ago Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer Analog/Mixed Signal ASIC Design Engineer Analog/Mixed Signal ASIC Design Engineer Validation Engineer with DDR Familiarity We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

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