Physical Design Engineer (SoC)

New Today

Description : • Perform physical implementation in Synopsys tools (ICC2) • Develop and maintain the tool flow to support the project. • Work with Team to enhance PD methodology. • Fixing DRC/LVS issues • Fixing voltage drop violations • Timing ECOs
Requirements: • Experience in advanced node processes 16nm and below. • Experience with industry-standard tools, preference for Synopsys flow. • Understanding of Implementation flow · Understanding of timing constraints and static timing analysis (STA). • Experience with Calibre for DRC/LVS checks, and automation through scripting such as Perl, Python, Tcl & Make.
IND 123
Location:
San Jose

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