Principal Design Engineer

New Yesterday

onsemi is seeking an energetic, motivated professional to join their product development team located in Richardson, Texas. You will join a cohesive group of experienced designers with a wide range of industry experience who cultivate a “customer first” culture and friendly working environment. Projects will require you to work with cross-functional teams comprised of logic and IP design, physical implementation, packaging, test, and product engineering. As a Principal design engineer, you will design custom ASICs and ASSPs with tasks spanning design concept to chip tape-out. Tasks include: Verilog RTL coding Design-for-Test Static Timing Analysis in a variety of technologies Logical and/or physical synthesis UPF creation and low-power design Analysis and design of complex timing and clock interfaces IP integration, including analog content for mixed-signal design ATPG and simulation As a principal engineer, responsibilities include technical leadership, project planning, and resource management. You will collaborate to find solutions for problems that occur during the design process and communicate directly with internal and external customers on design status and technical implementation. You will mentor junior engineers and provide training and guidance for a variety of design tasks while maintaining a growth mindset with regard to your own professional development.
Required Qualifications PhD, MS or BS in Electrical Engineering, or Computer Engineering Familiarity with design concepts and architectures for complex digital and mixed-signal circuits Full understanding of digital and mixed-signal design flows; 10+ years of experience preferred. Experience with logic synthesis using Synopsys Design Compiler or related tools; Physical synthesis a plus RTL coding experience Experience with static timing analysis using Synopsys Primetime or related tools Experience with the Siemens Tessent DFT tool suite or related tools Experience with Spyglass or other related audit tools for LINT and CDC Experience with developing simple verilog test benches. Experience with Synopsys, Mentor, or Cadence simulation tools In depth knowledge of hierarchical and low power design techniques. Experience with version control systems and methodologies (., branching, tagging) Superior writing, grammar, and verbal communication skills Excellent analytical/debugging skills Willingness to work in highly visible and dynamic environment Ability to work independently and with team members local or remote. Preferred Qualifications Experience with advanced verification platforms (UVM) Knowledge and experience in vetting and deploying sophisticated EDA software flows Familiarity with APAR design techniques or tool suites 'Employment at onsemi is contingent on providing verification of work authorization and verification of . Person status (., . citizens, permanent residents, and other protected individuals under the Immigration and Naturalization Act, 8 . 1324b(a)(3)) or obtaining any necessary license for roles requiring access to hardware, software, services, or technical data controlled by . export control laws and regulations'
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Location:
Allen

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