Principal Memory Design Engineer/ Senior Technical Manager Primary responsibilities include collaborating with tier-1 ASIC customers in North America to co-design embedded memory architectures and circuits in advanced nodes.

Make your application after reading the following skill and qualification requirements for this position. Work closely with product and architecture teams to define, design, and develop high-performance customized semiconductor memories such as SRAM, TCAM, CPU caches, and Compute-In-Memory (CIM) macros, addressing varied PPA requirements across Cloud AI, Networking, Automotive, and edge AI applications. Design dual-rail custom memories from start to finish to meet customer PPA specifications. Innovate and incorporate special circuits and features to achieve top-tier PPA for custom and compiler memories. Mentor and guide other designers, while actively engaging in digital circuit design, especially for memories. Be highly organized and independent, capable of multitasking and collaborating with global design and CAD teams. Requirements 12+ years of hands-on experience in designing embedded memories (SRAM, TCAM) for high-performance processors or ASICs in advanced nodes (3nm/5nm). Proven track record of innovative solutions (papers, patents), with a good understanding of the technology roadmap and market trends for embedded memories. Strong understanding of digital circuit design techniques in FinFET technologies. Experience with the complete design cycle of SRAM memory and compiler development. Supervision of layout engineers and review of layout for optimality. Ability to develop comprehensive design verification and silicon bring-up plans for high-performance embedded memories. Experience with LEC tools (ESPCV). Ability to review and coordinate layout activities. Silicon debug and bring-up experience is required. Working knowledge of scripting in Perl/Python. Willingness to collaborate closely with cross-functional teams globally.

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