Description Acara Solutions has been providing advanced manufacturing and technology firms our staffing related services since the 1950's. Our San Diego (or San Jose) low power wireless technology client is looking for a Principal SoC Full-Chip Physical Design Implementation & Verification Engineer  to join their organization as a direct salaried employee. The base salary target is $220K with possible flexibility up to $240K.  The key qualifications for this principal physical design engineer covers: Full chip floor planning, bump design, Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification. The entire SOC implementation and verification flow from RTL-to-GDS that includes full chip floor plan, place and route, CTS, and layout verification sign off on lower power SoC. The term RTL-to-GDS refers to the entire implementation flow that transforms a digital design described in RTL (Register Transfer Level) into a GDS (Graphic Data System) file - the final physical layout file sent to the semiconductor foundry for chip fabrication. This is the full SoC physical design flow , and it's central to what many principal-level SoC engineers are responsible for managing or guiding. We are seeking a highly experienced and innovative engineer to lead the full-chip implementation and verification of complex System-on-Chip (SoC) designs. This role involves overseeing the end-to-end process from RTL development through to post-silicon validation, ensuring the delivery of high-performance, reliable, and power-efficient SoCs. Key Responsibilities Full-Chip SoC Design & Implementation : Lead the architecture, microarchitecture, and RTL design of complex SoCs, collaborating with cross-functional teams to meet performance, power, and area (PPA) targets. Verification Strategy & Execution : Develop and execute comprehensive verification plans for full-chip integration, including top-level simulations, emulation, and formal verification techniques. Testbench Development : Design and implement scalable and reusable testbenches using SystemVerilog and UVM methodologies to validate SoC functionality. Debugging & Failure Analysis : Utilize advanced debugging tools and techniques to identify and resolve issues in RTL, testbenches, and simulation environments. Cross-Disciplinary Collaboration : Work closely with architecture, design, DFT, physical design, and software teams to ensure seamless integration and timely delivery of SoC projects. Job Requirements Required Skills / Qualifications:BSEE or MSEE and PhD a plus Min 10 years of SoC design and verification that includes the following:  Full chip floor planning, bump design, Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification. The entire SOC implementation and verification flow from RTL-to-GDS that includes full chip floor plan, place and route, CTS, and layout verification sign off on lower power SoC Preferred: Wireless low-power experience