Senior Mixed-Signal Design Verification Engineer Senior Mixed-Signal Design Verification Engineer 15 hours ago Be among the first 25 applicants Get AI-powered advice on this job and more exclusive features. Capgemini Engineering provided pay range This range is provided by Capgemini Engineering. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range $137,450.00/yr - $203,800.00/yr Direct message the job poster from Capgemini Engineering About the Job You’re Considering We’re looking for a collaborative Senior Mixed-Signal Design Verification Engineer to help shape the future of SoC development. In this role, you’ll contribute to the validation of high-performance ARM-based systems, working across digital and analog domains. You’ll join a supportive team that values diverse perspectives, continuous learning, and innovative problem-solving. Your Role Develop and implement verification environments using SystemVerilog and UVM for IPs and SoCs with embedded CPUs and mixed-signal interfaces. Contribute to AMS and power-aware verification efforts across multiple projects, ensuring robust and efficient validation. Create detailed test plans and coverage metrics from design specifications, and execute both block- and chip-level tests. Automate verification workflows using PERL and Python to streamline test generation and debugging. Collaborate with design engineers to analyze and resolve RTL and gate-level simulation issues. Validate low-power design intent using UPF or CPF through targeted test cases. Partner with architects to simulate real-world use cases and ensure system-level functionality. Your Skills and Experience Bachelor’s degree or higher in Electrical or Computer Engineering, with 7+ years of experience. Deep expertise in SystemVerilog, UVM, and SV Assertions, with a strong foundation in Verilog-HDL and scripting. Proven success in verifying ARM Cortex-based SoCs and working with interfaces such as GPIO, UART, SPI, SW, JTAG, and I2C. Proficient with Cadence tools (NCVerilog, NCSIM, Simvision), AMS simulation environments, and experience with SDF-annotated simulations and linting tools. Strong analytical and communication skills, with a self-driven, collaborative approach to problem-solving and automation using Python and PERL. Seniority level Seniority level Mid-Senior level Employment type Employment type Full-time Job function Job function Consulting and Engineering Industries IT Services and IT Consulting Referrals increase your chances of interviewing at Capgemini Engineering by 2x Inferred from the description for this job 401(k) Disability insurance Medical insurance Vision insurance Get notified about new Design Verification Engineer jobs in Santa Clara, CA . Sunnyvale, CA $114,000.00-$166,000.00 2 days ago San Jose, CA $136,000.00-$204,000.00 1 week ago San Jose, CA $136,000.00-$204,000.00 1 week ago San Jose, CA $108,400.00-$154,200.00 2 weeks ago Mountain View, CA $113,000.00-$161,000.00 2 weeks ago Sunnyvale, CA $114,000.00-$166,000.00 1 day ago San Jose, CA $165,700.00-$232,900.00 12 hours ago Sunnyvale, CA $142,000.00-$203,000.00 2 days ago Physical Design and Verification Engineer Design Verification Engineer (Fulltime role only) Sunnyvale, CA $190,000.00-$200,000.00 1 day ago San Jose, CA $133,300.00-$186,800.00 1 week ago Sunnyvale, CA $173,000.00-$249,000.00 2 days ago CPU Verification Engineer (Multiple Locations) Cupertino, CA $104,000.00-$212,200.00 2 weeks ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

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