Company DescriptionRISC-V is an Instruction Set Architecture (ISA) standard enabling a new era of processor innovation through open collaboration. RISC-V International enables the community to share technical investment, contribute to the strategic future, create more rapidly, enjoy unprecedented design freedom, and substantially reduce the cost of innovation.RISC-V International, a non-profit organization controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of RISC-V International have access to and participate in the development of the RISC-V ISA specifications and related ecosystem.This role is a full-time contract opportunity, dedicated to RISC-V International. Individual and service companies are encouraged to apply. It will start with a 6-month contract, with potential extension in 1-year increments.To learn more about RISC-V, please visit: www.riscv.org.RISC-V International is seeking a mid-Senior level Verification Engineer to join the technical team, focusing on certification program test architecture and development.Time will be billed hourly, with a maximum of 40 hours/week. The expected salary range is $12,000 to $14,000 per month, based on experience.Key Responsibilities:Collaborate with the RISC-V International Technical Team and the RISC-V CSC community to build and deliver certification tests and test plans.Participate in RISC-V Certification Steering Committee (CSC) and work group meetings; support test case and test plan development and maintenance.Establish and maintain simulation environments for Sail, Spike, QEMU, and others as needed, to meet CSC requirements for test evaluation and development.Develop tools-based, repeatable processes for evaluating test case coverage using SystemVerilog-based coverage tools.Assess and report on open source test suite readiness for certification testing.Collaborate with open source test suite communities to improve test coverage through development and maintenance.Create and review documentation for test setup and execution of selected test suites.Qualifications:BSc/BA in EE or ECE.5+ years of experience developing processor verification tests.Proficiency with UNIX/Linux scripting tools (make, bash, perl, Python).Experience with industry standards, specifications, interoperability, and compliance test plans.Experience with coverage-driven verification testing.Experience with instruction set simulators (ISS).Proficiency in SystemVerilog.Experience in verification testing across silicon, simulators, and FPGA environments.Experience with GitHub, including CI/regression test automation.Experience working in collaborative, community-driven environments.Leadership experience in collaborative groups with diverse skill levels.Ability to respond and adapt in interrupt-driven environments.Effective time management, goal setting, and communication skills.Excellent written and verbal communication skills, concise and clear.Attention to detail in content and presentation.Preferred Skills:Master's or PhD in EE or ECE.Experience with RISC-V ISA and assembly language.Experience with QEMU, Spike, or Sail simulators.Involvement in open source software and hardware communities.Additional InformationAll information will be kept confidential according to EEO guidelines. #J-18808-Ljbffr