Summary Join an ambitious, experienced team of silicon and distributed systems experts as a design verification engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers. We are looking for talented, motivated candidates with experience building comprehensive verification frameworks and executing simulation test plans for large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. Default location is Mountain View, CA, but we are equally open to remote candidates. Roles & Responsibilities Work in the SOC DV team to perform end to end verification of a large SOC. Define and review a comprehensive SOC verification plan, including the test strategy, specific test cases, and coverage metrics. Cover various aspects of SOC verification, including functional testing, integration verification, performance verification etc. Key Qualifications Experience with large SOC verification. Familiar with SystemVerilog/UVM Minimum 3 years of experience in the ASIC verification field Experience with block to SOC verification reuse methodology is a plus. Experience with firmware based verification is a plus Experience with large scale SOC TB performance optimization is a plus Experience with high speed interface protocol like PCIE/CXL/DDR/Ethernet is a plus Experience with ARM SOC bring up is a plus.