Wireless SOC Design Verification Engineer As part of our team, you will have the opportunity to verify complex SOCs. Our team integrates multiple sophisticated IP level DV environments, crafts highly reusable best-in-class UVM Testbenches, implements effective coverage-driven and directed test cases, deploys new tools, and adopts methodologies to improve tape-out readiness. By collaborating with other product development groups across Apple, you can push the industry boundaries of wireless systems and enhance the product experience for our customers worldwide.

The following information aims to provide potential candidates with a better understanding of the requirements for this role. You will learn all aspects of large-scale SOCs, different architectures, high-speed layered protocols, low power methodologies, and wireless protocols. You will gain knowledge of FW-HW interactions and multi-chip SOC debug architectures. As a Design Verification Engineer, you'll be central to verifying our silicon designs, responsible for pre-silicon RTL verification of blocks and top-level SOCs. The role requires thriving in a dynamic, multi-functional environment, debating ideas openly, and delivering on complex wireless protocol requirements. Description Understand high-efficiency SOC architecture, standard peripherals such as PCIe, Power Management & Low-Power schemes, DMA, CPUs, DDR, USB, PLL, power-up sequences, and Secured Boot schemes. Deliver power management designs using low-power methodologies and UPF simulations. Develop coverage-driven verification plans from specifications, review, and refine to meet coverage targets. Architect UVM-based highly reusable test benches, integrating complex VIPs, sub-system test benches, and test suites at the SOC level. Achieve targeted coverage and collaborate with design, architecture, software, firmware, and external IP teams to verify the overall SOC design. Work closely with DV methodology architects to improve verification metrics. Minimum Qualifications BS degree and at least 10 years of relevant industry experience. Preferred Qualifications Hands-on ASIC & SOC DV experience. Sophisticated knowledge of HVL methodology (UVM/OVM), with recent UVM experience. Experience with formal verification is a plus. Proven track record across full ASIC cycle from concept to tape-out, including test planning, testbench implementation, test creation, debugging, and coverage closure. Experience taping out large SOC systems with embedded processors. Verification experience with PCIe, Bus Fabric, NOC, AHB, AXI in UVM environments. Deep knowledge of low power design, UPF integration, boot-up, power cycling, and HW/FW interaction verification. Low Power Verification experience is a plus. Excellent communication, problem-solving skills, and a collaborative mindset. At Apple, base pay ranges from $171,600 to $302,200, depending on skills, experience, and location. Employees may participate in stock programs, receive benefits like medical coverage, retirement plans, discounts, educational reimbursements, and may be eligible for bonuses or relocation assistance. Apple is an equal opportunity employer committed to diversity and inclusion. #J-18808-Ljbffr