Advanced Packaging Engineer
New Today
Responsibilities of the Advanced Packaging Engineer:
- Lead development of test vehicles and packaging flows for multi-die architectures (e.g., CoWoS, bridge-based, MCM)
- Drive integration of packaging into system designs (thermal, electrical, mechanical alignment)
- Collaborate with foundries and OSATs to oversee tooling, materials, and process readiness
- Guide early learning, DFM/DFY/DFR implementation, risk mitigation, and qualification planning
- Support failure analysis and root cause investigations for material and yield issues
- Define integration best practices, material specs, and reliability requirements
- Present status, risks, and strategy updates to leadership and external partners
Requirements for the Advanced Packaging Engineer:
- Bachelor's in Mechanical, Electrical, or Chemical Engineering; Master's a plus
- 15+ years in advanced IC packaging development, with deep CoWoS expertise
- System-level knowledge of packaging integration (power, signal, thermals)
- Familiar with substrate/interposer technologies, multi-die co-design, and 3D stacking (preferred)
- Experience with test vehicles, fine-pitch interconnects, and material evaluation
- Proven collaboration with TSMC and/or other global foundries
- Strong analytical, organizational, and cross-functional communication skills
Compensation for the Packet Processor Architect:
- $190,000-$270,000
- Comprehensive Benefits: Health, Vision, Dental, PTO, Paid Holiday, Sick Leave if Required by Law
Keywords: advanced packaging engineer, CoWoS, 2.5D integration, multi-die packaging, chiplet integration, test vehicles, daisy chain networks, substrate technology, interposer, fine-pitch interconnects, system integration, mechanical engineering, electrical engineering, material science, 3D stacking, TSMC, OSAT, packaging development, package-to-system integration, package qualification, die attach, microbump bonding, wafer-level assembly, underfill, molding, thermal analysis, reliability testing, DFM, DFY, DFR, FMEA, yield improvement, packaging process optimization, volume production, semiconductor packaging, IC packaging, packaging design, advanced IC packaging, San Jose, semiconductor materials
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This job opens for applications on 7/25/2025. Applications for this job will be accepted for at least 30 days from the posting date.
- Location:
- Saratoga
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