Analog Mixed-Signal Design Engineer

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Broadcom is looking for a senior level analog mixed-signal designer. In this highly visible role, you will be designing high-speed analog mixed-signal circuitry for AI data center connectivity products.
MS or PhD in Electrical Engineering or Computer Engineering with 8+ years of high-speed analog mixed signal design in advanced CMOS nodes. Experience in designing low jitter, low power PLL, VCO and clocking circuitry. Experience with analog or ADC based Clock and Data Recovery (CDR) is desirable. Good understanding of advanced clock distribution techniques such as resonant and traveling wave clocking. Experience with designing analog front end circuits such as data converters, clock drivers and Trans-Impedance Amplifiers (TIA) in advanced CMOS nodes. Proficiency in electromagnetic tools like EMX or similar. Familiarity with behavioral modeling tools such as Matlab, SimuLink, VerilogA, Verilog. Good understanding of high-speed analog mixed-signal design trade-offs to drive attainment on metrics such as power, jitter and timing budget. Experience in assessing design bugs and recommending fixes or workarounds to balance technical requirements with schedule. Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals. Good understanding of signal integrity and power integrity. Good understanding of design tape-out to foundries and solid understanding of supply chain for ASIC product development. Strong analytical thinking and problem-solving skills with excellent attention to details. Must be organized, self-motivated and able to work effectively across internal and end customers teams. Must have good knowledge/experience with TSMC 7nm-5nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.
Job Description:
Broadcom is looking for a senior level analog mixed-signal designer. In this highly visible role, you will be designing high-speed analog mixed-signal circuitry for AI data center connectivity products.
Qualifications include:
MS or PhD in Electrical Engineering or Computer Engineering with 8+ years of high-speed analog mixed signal design in advanced CMOS nodes. Experience in designing low jitter, low power PLL, VCO and clocking circuitry. Experience with analog or ADC based Clock and Data Recovery (CDR) is desirable. Good understanding of advanced clock distribution techniques such as resonant and traveling wave clocking. Experience with designing analog front end circuits such as data converters, clock drivers and Trans-Impedance Amplifiers (TIA) in advanced CMOS nodes. Proficiency in electromagnetic tools like EMX or similar. Familiarity with behavioral modeling tools such as Matlab, SimuLink, VerilogA, Verilog. Good understanding of high-speed analog mixed-signal design trade-offs to drive attainment on metrics such as power, jitter and timing budget. Experience in assessing design bugs and recommending fixes or workarounds to balance technical requirements with schedule. Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals. Good understanding of signal integrity and power integrity. Good understanding of design tape-out to foundries and solid understanding of supply chain for ASIC product development. Strong analytical thinking and problem-solving skills with excellent attention to details. Must be organized, self-motivated and able to work effectively across internal and end customers teams. Must have good knowledge/experience with TSMC 7nm-5nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.
Highly Desired Qualifications:
Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels. Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results. Excellent time and task management, and interpersonal skills.
Additional Job Description:
Compensation And Benefits
The annual base salary range for this position is $120,000 - $192,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
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Location:
San Jose, CA
Salary:
$200
Category:
Engineering

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