We Are: At Synopsys, we drive innovations that shape how we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. Join us to transform the future through continuous innovation. You Are: You are a skilled ASIC Physical Design Engineer with a passion for technology. You excel in backend ASIC design from netlist to GDSII and physical verification for standard cell libraries. You create hard macros for advanced nodes and debug physical verification results. A collaborative team player, you guide junior peers and provide valuable customer feedback. What You’ll Be Doing: Developing backend ASIC design flow from netlist to GDSII & physical verification. Creating hard macros for Logic Libraries Testchips. Debugging physical verification results. Collaborating with cross-functional teams. Guiding and mentoring junior peers. Providing feedback to customers. The Impact You Will Have: Ensure successful standard cell library validation. Contribute to high-performance silicon chip creation. Drive innovation in ASIC physical design. What You’ll Need: Bachelor's or Master's degree in electronics/electrical engineering. 2+ years of related experience. Deep understanding of VLSI technology and digital design flow. Proficiency in PnR tool technology files/options. Who You Are: Excellent communicator with strong interpersonal skills. Collaborative team player. Proactive problem-solver. The Team You’ll Be A Part Of: Join a dynamic team focused on advancing ASIC physical design. We push technological boundaries and ensure high standards of quality and performance, fostering an inclusive and supportive work environment. Rewards and Benefits: We offer comprehensive health, wellness, and financial benefits. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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