Design Verification Engineer

At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. This role is for a digital-focused DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Minimum Qualifications

BS Degree is required.

Preferred Qualifications

Deep knowledge of SystemVerilog and UVM. Deep knowledge in developing scalable and portable test-benches. Proven experience with verification methodologies and tools such as simulators, waveform viewers. Build and run automation, coverage collection, gate level simulations. Some UVM knowledge, C/C++ level knowledge. Deep experience with serial protocols such as PCIe or USB, parallel protocol such as DDR. Basic knowledge of formal verification methodology. Some experience with power-aware (UPF) or similar verification methodology. Knowledge of one of the scripting languages such as Python, Perl, TCL.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics.