IP Silicon Design Verification Engineer page is loadedIP Silicon Design Verification EngineerApply locations San Jose, California, United States time type Full time posted on Posted 5 Days Ago job requisition id R01101 Job Details: Job Description:

The experience expected from applicants, as well as additional skills and qualifications needed for this job are listed below. Performs functional logic verification of an FPGA to ensure design will meet specification requirements.

Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.

Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs.

Replicates, root causes, and debugs issues in the pre-silicon environment.

Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.

May also collaborate with systems and software engineers to support integration testing of the FPGA.

Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.

Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.

Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $140k - $190k USD Qualifications: BS in Electrical Engineering, Computer Science or related field

5+ years experience

Understanding of UVM based verification techniques and other modern methods for design verification

Demonstrated ability to understand complex IP designs and debug RTL working closely with design teams.

Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Similar Jobs (5)Silicon Design Verification Engineerlocations San Jose, California, United States time type Full time posted on Posted 5 Days AgoPrincipal Engineer, IP Design Verificationlocations San Jose, California, United States time type Full time posted on Posted 5 Days AgoFPGA Silicon Design Engineerlocations San Jose, California, United States time type Full time posted on Posted 30+ Days Ago Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Ourend-to-endbroad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet. Don't see the dream job you are looking for? Click " Get Started " below to drop off your contact information and resume and we will reach out to you if we find the perfect fit.

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