Primary Responsibilities:

• Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams
• Chip/Block Level Floor planning and pin assignment
• Review top-level/block-level clock specifications for completeness and feasibility
• Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing)
• Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification)
• Presentations and Customer Interaction in customer meetings

Necessary Qualifications:

• BSEE, with 5+ years of experience or equivalent experience. MSEE preferred.
• Experience in ASIC Physical Design; Experience in an SoC product development organization with tape outs at 28nm/16nm design nodes.
• Hands-on Experience with implementation EDA tools like ICC2/Innova's.
• Scripting (Perl/Tcl/Python) is required.
• Good understanding of ASIC frontend design.
• Experience in both Flat and Hierarchical layouts.
• Strong problem-solving skills and ability to analyze and resolve physical design issues related to library, timing constraints or CAD tools is required.
• Experience with power analysis and IR-drop tools (prime power/Redhawk) and Static Timing Analysis (Primetime).
• Experience with Physical Verification and fix PV errors in layout.
• Expert handling of Verilog HDL based Netlists, Physical design libraries.
• Team player with good interpersonal and communication skills; ability to explain processes and answer customer questions during meetings.

Primary Responsibilities:

• Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams
• Chip/Block Level Floor planning and pin assignment
• Review top-level/block-level clock specifications for completeness and feasibility
• Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing)
• Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification)
• Presentations and Customer Interaction in customer meetings

Necessary Qualifications:

• BSEE, with 5+ years of experience or equivalent experience. MSEE preferred.
• Experience in ASIC Physical Design; Experience in an SoC product development organization with tape outs at 28nm/16nm design nodes.
• Hands-on Experience with implementation EDA tools like ICC2/Innova's.
• Scripting (Perl/Tcl/Python) is required.
• Good understanding of ASIC frontend design.
• Experience in both Flat and Hierarchical layouts.
• Strong problem-solving skills and ability to analyze and resolve physical design issues related to library, timing constraints or CAD tools is required.
• Experience with power analysis and IR-drop tools (prime power/Redhawk) and Static Timing Analysis (Primetime).
• Experience with Physical Verification and fix PV errors in layout.
• Expert handling of Verilog HDL based Netlists, Physical design libraries.
• Team player with good interpersonal and communication skills; ability to explain processes and answer customer questions during meetings.

Skills and Certifications& [note: bold skills and certification are required]
Pre-layout STA to ascertain feasibility, timing constraint validation, Chip/Block Level Floor plan
Experience in ASIC Physical Design; Experience in an SoC product,
hysical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing)
Scripting (Perl/Tcl/Python)