Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

Find out if this opportunity is a good fit by reading all of the information that follows below. Efficient is hiring a Senior ASIC Physical Design Engineer with experience in backend implementation from Netlist to GDSII. We seek individuals to leverage low‑power techniques and design-technology co‑optimization in advanced technology nodes to build energy‑efficient SoCs. This is a unique opportunity to get in at the ground level and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond! Key Responsibilities Take ownership of the physical design of multi-hierarchy low-power designs in advanced technology nodes. This includes executing physical-aware logical synthesis, floor planning, place and route, clock tree synthesis, static timing analysis, ERC, IR drop analysis, electromagnetic analysis, and physical verification. Analyze, debug and fix placement-, cts-, routing-, and buffering- related design and flow issues, using semi-custom placement, route guides and other tool directives via scripts to converge design to PPA targets. Own and deliver designs meeting sign-off timing targets (setup/hold across multiple corners with OCV derating) within specified power envelope while managing constraints (sdc). Lead the integration of the partition/IP, analyze port, feedthrough, macro placements, review DRV, LVS, IR violations and adjust collateral for clean integration. Engage with the digital design team to understand the architecture to address congestion and timing issues through design modifications and functional Engineering Change Orders (ECOs). Engage with the DFT team to plan and provide early feedback on design decisions that relate to physical implementation. Create scripts for EDA tools to automate tasks and enhance the throughput and quality of the physical design process. Required Qualifications Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience. Proven track record of delivering block (or SoC) RTL2GDSII for multiple tape-outs in 22nm or below process technologies. Experience with EDA flow using Cadence/Synopsys/Mentor tools for front‑end (Synthesis/LEC), back‑end (Place and Route), and verification/simulation (Physical Verification) with hierarchical design and abstraction techniques. Hands-on experience in place & route, power and clock-tree implementation, and timing convergence of high-frequency designs. Knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions. Experience with low power implementation typical in industry, including advanced knowledge of UPF standard (IEEE-1801). Excellent scripting skills in TCL, Bash and python. Preferred Qualifications Experience in full chip floor planning, partitioning, budgeting, and power grid planning. Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design. Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers. Knowledge of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions. Experience in validating Power Distribution Networks from package to pg grid, IR/EM: static and dynamic. Experience in integrating analog or mixed-signal macro on top-level design. We offer a competitive salary for this role, generally ranging from $180,000 to $210,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate. Why Join Efficient? At Efficient, we do not care about hierarchy—your impact is what matters. If you produce prodigious, high-quality work, you will be recognized and rewarded accordingly. We are a high-trust, high-output team where ownership and autonomy are paramount. If you are looking for a career-defining opportunity to shape the future of high-performance computing, let’s talk. Efficient offers a competitive compensation and benefits package , including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility . We are committed to personal and professional development and strive to grow together as people and as a company.

#J-18808-Ljbffr