Principal Digital Design Engineer, San Jose

Principal Digital Design Engineer

2 Days Old

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com

Job Description

We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc.
Basic Qualifications:

Strong academic and technical background in electrical engineering. A Bachelor's degree in EE is required, and a Master's degree is preferred.
8 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
Authorized to work in the US and start immediately.

Required Experience:

Hands-on, thorough knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
Proven front end design expertise - architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
Experience with Cadence and/or Synopsys digital design tools/flows
Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
Familiarity with UVM based design verification
Silicon bring-up and debug expertise
Small-geometry CMOS (≤28nm) design

Preferred Experience:

Firmware development with C-language, scripting with Python or other equivalent programming languages.
Development/support for PCIe or Ethernet Switch products.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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Location:: San Jose

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