SDC/STA Engineer
New Today
Role: SDC/STA Engineer
Location: San Jose, CA (Onsite)
Duration: Fullt- time
Required Skills: Synopsys, block/full chip SDC development
Job Description:
What will you do:
•Being a member of design team who oversees full chip SDCs and works with physical design and DFT teams to close full chip timing in multiple timing modes.
•Option to also do block level RTL design or block or top-level IP integration.
•Helping develops efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
•Helping develop and apply methodology to ensure correctness and quality of SDCs .
•Reviewing block level SDCs and clocking diagrams and mentoring other RTL design owners on SDC development.
•Creating fullchip clocking diagrams and related documentation.
What we are looking for:
•Experience with block/full chip SDC development in functional and test modes.
•Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
•Understanding of related digital design concepts (eg. clocking and async boundaries)
•Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming.
•Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)
•Experience with Spyglass CDC and glitch analysis
•Experience using Formal Verification: Synopsys Formality and Cadence LEC.
•Experience with scripting languages such as Python, Perl, or TCL
For more information and other jobs available please contact our recruitment team at careers@tekfortune.com. To view all the jobs available in the USA and Asia please visit our website at https://www.tekfortune.com/careers/.
- Location:
- San Jose