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Want to apply Read all the information about this position below, then hit the apply button. Must have / Primary skills : Fullchip timing, SDC changes back to block level, Block / Full chip SDC development, Static Timing Analysis, Primetime / Tempus WhatYou'llBeDoing : Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop efficient methodology to promote block level SDCs to fullchip , and to bring fullchip SDC changes back to block level. Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle. Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development. Creating fullchip clocking diagrams and related documentation. What We Are Looking For : Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master's Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience. Experience with block / full chip SDC development in functional and test modes. Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime / Tempus Understanding of related digital design concepts (eg. clocking and async boundaries) Experience with synthesis tools (eg. Synopsys DC / DCG / FC), Verilog / System Verilog programming Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence) Experience with Spyglass CDC and glitch analysis Experience using Formal Verification : Synopsys Formality and Cadence LEC. Experience with scripting languages such as Python, Perl, or TCL We are looking for strong hands-on experience in 3 areas SDC : / Design Constraints and STA : Timing Analysis (PrimeTime ) : Very good knowledge in writing Timing Constraints with these tools Digital Circuits : Person should be very strong in Design Fundamentals so can make right changes in RTL as needed Bridge : He needsto act as a bridge between Design & Physical Design team and provide solutions to meet timings through constraints PD Tools : Nice to have but not must have floor-planning and P&R flow work Seniority level Seniority level Mid-Senior level Employment type Employment type Contract Job function Job function Engineering and Information Technology Staffing and Recruiting Referrals increase your chances of interviewing at Prismagic Solutions Inc. by 2x Get notified about new Senior Design Engineer jobs in San Jose, CA Sunnyvale, CA $170,000 - $240,000 1 week ago Sunnyvale, CA $204,000 - $281,000 5 days ago Pleasanton, CA $190,000 - $220,000 2 hours ago San Francisco Bay Area $180,000 - $240,000 2 weeks ago Santa Clara, CA $247,000 - $260,000 2 days ago Senior Digital / Mixed-Signal IC Design Engineer Sr. Design for Reliability Manager - Mechanical Systems Palo Alto, CA $237,200 - $296,500 2 weeks ago Software Engineering Manager - AI Hardware Systems Co-Design Sunnyvale, CA $177,000 - $251,000 5 days ago Mountain View, CA $183,000 - $271,000 16 hours ago Sr. Mechanical Design Engineer, Power Electronics Palo Alto, CA $106,400 - $206,520 11 hours ago Mountain View, CA $178,000 - $265,000 16 hours ago We're unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI. J-18808-Ljbffr Create a job alert for this search Senior Design Engineer • San Jose, CA, US

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